A Content – Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique

Abstract

© 2018 IEEE.Modern high-energy physics experiments such as the Compact Muon Solenoid experiment at CERN produce an extraordinary amount of data every 25ns. To handle a data rate of more than 50Tbit/s a multi-level trigger system is required, which reduces the data rate. Due to the increased luminosity after the Phase-II-Upgrade of the LHC, the CMS tracking system has to be redesigned. The current trigger system is unable to handle the resulting amount of data after this upgrade. Because of the latency of a few microseconds the Level 1 Track Trigger has to be implemented in hardware. State-of-the-art pattern recognition filter the incoming data by template matching on ASICs with a content addressable memory architecture. A first implementation on an FPGA, which replaces the content addressable memory of the ASIC, has been developed. This design combines the advantages of a content addressable memory and an efficient utilization of the logics elements of an FPGA. This paper presents an extension of this FPGA design, which is based on the idea of data compression and assemble the stored data to appropriate packages and drastically reduces the required number of write and read cycles. Furthermore, the extended design meets the strong timing constraints, possesses the required properties of the content addressable memory and enabled a compressed storage of an increased amount of data.