Bergmann T., Balzer M., Bormann D., Chilingaryan S.A., Eitel K., Kleifges M., Kopmann A., Kozlov V., Menshikov A., Siebenborn B., Tcherniakhovski D., Vogelgesang M., Weber M.
in 2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2015 (2016), 7581841. DOI:10.1109/NSSMIC.2015.7581841
© 2015 IEEE. The EDELWEISS experiment, located in the underground laboratory LSM (France), is one of the leading experiments using cryogenic germanium (Ge) detectors for a direct search for dark matter. For the EDELWEISS-III phase, a new scalable data acquisition (DAQ) system was designed and built, based on the ‘IPE4 DAQ system’, which has already been used for several experiments in astroparticle physics.
Harbaum T., Seboui M., Balzer M., Becker J., Weber M.
in Proceedings – 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016 (2016) 184-191, 7544775. DOI:10.1109/FCCM.2016.52
© 2016 IEEE. Modern high-energy physics experiments such as the Compact Muon Solenoid experiment at CERN produce an extraordinary amount of data every 25ns. To handle a data rate of more than 50Tbit/s a multi-level trigger system is required, which reduces the data rate. Due to the increased luminosity after the Phase-II-Upgrade of the LHC, the CMS tracking system has to be redesigned. The current trigger system is unable to handle the resulting amount of data after this upgrade. Because of the latency of a few microseconds the Level 1 Track Trigger has to be implemented in hardware. State-of-the-art pattern recognition filter the incoming data by template matching on ASICs with a content addressable memory architecture. An implementation on an FPGA, which replaces the content addressable memory of the ASIC, has not been possible so far. This paper presents a new approach to a content addressable memory architecture, which allows an implementation of an FPGA based design. By combining filtering and track finding on an FPGA design, there are many possibilities of adjusting the two algorithms to each other. There is more flexibility enabled by the FPGA architecture in contrast to the ASIC. The presented design minimizes the stored data by logic to optimally utilize the available resources of an FPGA. Furthermore, the developed design meets the strong timing constraints and possesses the required properties of the content addressable memory.
Amstutz C. et al.
in 2016 IEEE-NPSS Real Time Conference, RT 2016 (2016), 7543110. DOI:10.1109/RTC.2016.7543110
© 2016 IEEE.The CMS collaboration is preparing a major upgrade of its detector, so it can operate during the high luminosity run of the LHC from 2026. The upgraded tracker electronics will reconstruct the trajectories of charged particles within a latency of a few microseconds, so that they can be used by the level-1 trigger. An emulation framework, CIDAF, has been developed to provide a reference for a proposed FPGA-based implementation of this track finder, which employs a Time-Multiplexed (TM) technique for data processing.
Amstutz C. et al.
in 2016 IEEE-NPSS Real Time Conference, RT 2016 (2016), 7543102. DOI:10.1109/RTC.2016.7543102
© 2016 IEEE.A new tracking system is under development for operation in the CMS experiment at the High Luminosity LHC. It includes an outer tracker which will construct stubs, built by correlating clusters in two closely spaced sensor layers for the rejection of hits from low transverse momentum tracks, and transmit them off-detector at 40 MHz. If tracker data is to contribute to keeping the Level-1 trigger rate at around 750 kHz under increased luminosity, a crucial component of the upgrade will be the ability to identify tracks with transverse momentum above 3 GeV/c by building tracks out of stubs. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are identified using a projective binning algorithm based on the Hough Transform. A hardware system based on the MP7 MicroTCA processing card has been assembled, demonstrating a realistic slice of the track finder in order to help gauge the performance and requirements for a full system. This paper outlines the system architecture and algorithms employed, highlighting some of the first results from the hardware demonstrator and discusses the prospects and performance of the completed track finder.
Rota L., Balzer M., Caselle M., Kudella S., Weber M., Mozzanica A., Hiller N., Nasse M.J., Niehues G., Schonfeldt P., Gerth C., Steffen B., Walther S., Makowski D., Mielczarek A.
in 2016 IEEE-NPSS Real Time Conference, RT 2016 (2016), 7543157. DOI:10.1109/RTC.2016.7543157
© 2016 IEEE. We developed a fast linear array detector to improve the acquisition rate and the resolution of Electro-Optical Spectral Decoding (EOSD) experimental setups currently installed at several light sources. The system consists of a detector board, an FPGA readout board and a high-Throughput data link. InGaAs or Si sensors are used to detect near-infrared (NIR) or visible light. The data acquisition, the operation of the detector board and its synchronization with synchrotron machines are handled by the FPGA. The readout architecture is based on a high-Throughput PCI-Express data link. In this paper we describe the system and we present preliminary measurements taken at the ANKA storage ring. A line-rate of 2.7 Mlps (lines per second) has been demonstrated.
Rota L., Vogelgesang M., Perez L.E.A., Caselle M., Chilingaryan S., Dritschler T., Zilio N., Kopmann A., Balzer M., Weber M.
in Journal of Instrumentation, 11 (2016), P02007. DOI:10.1088/1748-0221/11/02/P02007
© 2016 IOP Publishing Ltd and Sissa Medialab srl.Modern physics experiments produce multi-GB/s data rates. Fast data links and high performance computing stages are required for continuous data acquisition and processing. Because of their intrinsic parallelism and computational power, GPUs emerged as an ideal solution to process this data in high performance computing applications. In this paper we present a high-throughput platform based on direct FPGA-GPU communication. The architecture consists of a Direct Memory Access (DMA) engine compatible with the Xilinx PCI-Express core, a Linux driver for register access, and high- level software to manage direct memory transfers using AMD’s DirectGMA technology. Measurements with a Gen3 x8 link show a throughput of 6.4 GB/s for transfers to GPU memory and 6.6 GB/s to system memory. We also assess the possibility of using the architecture in low latency systems: preliminary measurements show a round-trip latency as low as 1 μs for data transfers to system memory, while the additional latency introduced by OpenCL scheduling is the current limitation for GPU based systems. Our implementation is suitable for real-time DAQ system applications ranging from photon science and medical imaging to High Energy Physics (HEP) systems.
Caselle M., Blank T., Colombo F., Dierlamm A., Husemann U., Kudella S., Weber M.
in Journal of Instrumentation, 11 (2016), C01050. DOI:10.1088/1748-0221/11/01/C01050
© 2016 IOP Publishing Ltd and Sissa Medialab srl.In the next generation of collider experiments detectors will be challenged by unprecedented particle fluxes. Thus large detector arrays of highly pixelated detectors with minimal dead area will be required at reasonable costs. Bump-bonding of pixel detectors has been shown to be a major cost-driver. KIT is one of five production centers of the CMS barrel pixel detector for the Phase I Upgrade. In this contribution the SnPb bump-bonding process and the production yield is reported. In parallel to the production of the new CMS pixel detector, several alternatives to the expensive photolithography electroplating/electroless metal deposition technologies are developing. Recent progress and challenges faced in the development of bump-bonding technology based on gold-stud bonding by thin (15 μm) gold wire is presented. This technique allows producing metal bumps with diameters down to 30 μm without using photolithography processes, which are typically required to provide suitable under bump metallization. The short setup time for the bumping process makes gold-stud bump-bonding highly attractive (and affordable) for the flip-chipping of single prototype ICs, which is the main limitation of the current photolithography processes.
Steinmann J.L., Blomley E., Brosi M., Brundermann E., Caselle M., Hiller N., Kehrer B., Muller A.-S., Schedler M., Schonfeldt P., Schuh M., Schwarz M., Siegel M.
in IPAC 2016 – Proceedings of the 7th International Particle Accelerator Conference (2016) 2855-2857.
Copyright © 2016 CC-BY-3.0 and by the respective authors. We present the effects of the filling pattern structure in multi-bunch mode on the beam spectrum. This effects can be seen by all detectors whose resolution is better than the RF frequency, ranging from stripline and Schottky measurements to high resolution synchrotron radiation measurements. Our heterodyne measurements of the emitted coherent synchrotron radiation at 270 GHz reveal discrete frequency harmonics around the 100 000th revolution harmonic of ANKA, the synchrotron radiation facility in Karlsruhe, Germany. Significant effects of bunch spacing, gaps between bunch trains and variations in individual bunch currents on the emitted CSR spectrum are described by theory and supported by observations.
Brosi M., Steinmann J.L., Blomley E., Brundermann E., Caselle M., Hiller N., Kehrer B., Mathis Y.-L., Nasse M.J., Rota L., Schedler M., Schonfeldt P., Schuh M., Schwarz M., Weber M., Muller A.-S.
in Physical Review Special Topics – Accelerators and Beams, 19 (2016), 110701. DOI:10.1103/PhysRevAccelBeams.19.110701
© 2016, American Physical Society. All rights reserved. Dedicated optics with extremely short electron bunches enable synchrotron light sources to generate intense coherent THz radiation. The high degree of spatial compression in this so-called low-αc optics entails a complex longitudinal dynamics of the electron bunches, which can be probed studying the fluctuations in the emitted terahertz radiation caused by the microbunching instability (“bursting”). This article presents a “quasi-instantaneous” method for measuring the bursting characteristics by simultaneously collecting and evaluating the information from all bunches in a multibunch fill, reducing the measurement time from hours to seconds. This speed-up allows systematic studies of the bursting characteristics for various accelerator settings within a single fill of the machine, enabling a comprehensive comparison of the measured bursting thresholds with theoretical predictions by the bunched-beam theory. This paper introduces the method and presents first results obtained at the ANKA synchrotron radiation facility.
Vogelgesang M., Rota L., Perez L.E.A., Caselle M., Chilingaryan S., Kopmann A.
in Proceedings of SPIE – The International Society for Optical Engineering, 9967 (2016), 996715. DOI:10.1117/12.2237611
© Copyright 2016 SPIE. With ever-increasing data rates due to stronger light sources and better detectors, X-ray imaging experiments conducted at synchrotron beamlines face bandwidth and processing limitations that inhibit efficient workflows and prevent real-time operations. We propose an experiment platform comprised of programmable hardware and optimized software to lift these limitations and make beamline setups future-proof. The hardware consists of an FPGA-based data acquisition system with custom logic for data pre-processing and a PCIe data connection for transmission of currently up to 6.6 GB/s. Moreover, the accompanying firmware supports pushing data directly into GPU memory using AMD’s DirectGMA technology without crossing system memory first. The GPUs are used to pre-process projection data and reconstruct final volumetric data with OpenCL faster than possible with CPUs alone. Besides, more efficient use of resources this enables a real-time preview of a reconstruction for early quality assessment of both experiment setup and the investigated sample. The entire system is designed in a modular way and allows swapping all components, e.g. replacing our custom FPGA camera with a commercial system but keep reconstructing data with GPUs. Moreover, every component is accessible using a low-level C library or using a high-level Python interface in order to integrate these components in any legacy environment.