Rota L., Caselle M., Chilingaryan S., Kopmann A., Weber M.

in IEEE Transactions on Nuclear Science, 62 (2015) 972-976, 7111377. DOI:10.1109/TNS.2015.2426877

Abstract

© 2014 IEEE. We developed a direct memory access (DMA) engine compatible with the Xilinx PCI Express (PCIe) core to provide a high-performance and low-occupancy alternative to commercial solutions. In order to maximize the PCIe throughput while minimizing the FPGA resources utilization, the DMA engine adopts a novel strategy where the DMA address list is stored inside the FPGA and not in the central memory of the host CPU. The FPGA design package is complemented with simple register access to control the DMA engine by a Linux driver. The design is compatible with Xilinx FPGA Families 6 and 7, and operates with the Xilinx PCIe endpoint Generation 1 and 2 with all lane configurations (x1, x2, x4, x8). A multi-engine architecture is also presented, where two x8 lanes cores are used in parallel together with a PCIe bridge, to exploit fully the capabilities of a PCIe Gen2 x16 lanes link. A data throughput of 3461 MBytes/s has been achieved with a single PCIe Gen2 x8 lanes endpoint. If the dual-engine architecture is used, the throughput is increased up to 6920 MBytes/s. The presented DMA is currently used in several experiments at the ANKA synchrotron light source.

Stevanovic U., Caselle M., Cecilia A., Chilingaryan S., Farago T., Gasilov S., Herth A., Kopmann A., Vogelgesang M., Balzer M., Baumbach T., Weber M.

in IEEE Transactions on Nuclear Science, 62 (2015) 911-918, 7111386. DOI:10.1109/TNS.2015.2425911

Abstract

© 1963-2012 IEEE. High-speed X-ray imaging applications play a crucial role for non-destructive investigations of the dynamics in material science and biology. On-line data analysis is necessary for quality assurance and data-driven feedback, leading to a more efficent use of a beam time and increased data quality. In this article we present a smart camera platform with embedded Field Programmable Gate Array (FPGA) processing that is able to stream and process data continuously in real-time. The setup consists of a Complementary Metal-Oxide-Semiconductor (CMOS) sensor, an FPGA readout card, and a readout computer. It is seamlessly integrated in a new custom experiment control system called Concert that provides a more efficient way of operating a beamline by integrating device control, experiment process control, and data analysis. The potential of the embedded processing is demonstrated by implementing an image-based trigger. It records the temporal evolution of physical events with increased speed while maintaining the full field of view. The complete data acquisition system, with Concert and the smart camera platform was successfully integrated and used for fast X-ray imaging experiments at KIT’s synchrotron radiation facility ANKA.

Rota L., Caselle M., Chilingaryan S., Kopmann A., Weber M.

in IEEE Transactions on Nuclear Science, 62 (2015) 972-976, 7111377. DOI:10.1109/TNS.2015.2426877

Abstract

© 2014 IEEE.We developed a direct memory access (DMA) engine compatible with the Xilinx PCI Express (PCIe) core to provide a high-performance and low-occupancy alternative to commercial solutions. In order to maximize the PCIe throughput while minimizing the FPGA resources utilization, the DMA engine adopts a novel strategy where the DMA address list is stored inside the FPGA and not in the central memory of the host CPU. The FPGA design package is complemented with simple register access to control the DMA engine by a Linux driver. The design is compatible with Xilinx FPGA Families 6 and 7, and operates with the Xilinx PCIe endpoint Generation 1 and 2 with all lane configurations (x1, x2, x4, x8). A multi-engine architecture is also presented, where two x8 lanes cores are used in parallel together with a PCIe bridge, to exploit fully the capabilities of a PCIe Gen2 x16 lanes link. A data throughput of 3461 MBytes/s has been achieved with a single PCIe Gen2 x8 lanes endpoint. If the dual-engine architecture is used, the throughput is increased up to 6920 MBytes/s. The presented DMA is currently used in several experiments at the ANKA synchrotron light source.

Stevanovic U., Caselle M., Cecilia A., Chilingaryan S., Farago T., Gasilov S., Herth A., Kopmann A., Vogelgesang M., Balzer M., Baumbach T., Weber M.

in IEEE Transactions on Nuclear Science, 62 (2015) 911-918, 7111386. DOI:10.1109/TNS.2015.2425911

Abstract

© 1963-2012 IEEE.High-speed X-ray imaging applications play a crucial role for non-destructive investigations of the dynamics in material science and biology. On-line data analysis is necessary for quality assurance and data-driven feedback, leading to a more efficent use of a beam time and increased data quality. In this article we present a smart camera platform with embedded Field Programmable Gate Array (FPGA) processing that is able to stream and process data continuously in real-time. The setup consists of a Complementary Metal-Oxide-Semiconductor (CMOS) sensor, an FPGA readout card, and a readout computer. It is seamlessly integrated in a new custom experiment control system called Concert that provides a more efficient way of operating a beamline by integrating device control, experiment process control, and data analysis. The potential of the embedded processing is demonstrated by implementing an image-based trigger. It records the temporal evolution of physical events with increased speed while maintaining the full field of view. The complete data acquisition system, with Concert and the smart camera platform was successfully integrated and used for fast X-ray imaging experiments at KIT’s synchrotron radiation facility ANKA.

Rota L., Caselle M., Chilingaryan S., Kopmann A., Weber M.

in IEEE Transactions on Nuclear Science (2015). DOI:10.1109/TNS.2015.2426877

Abstract

We developed a direct memory access (DMA) engine compatible with the Xilinx PCI Express (PCIe) core to provide a high-performance and low-occupancy alternative to commercial solutions. In order to maximize the PCIe throughput while minimizing the FPGA resources utilization, the DMA engine adopts a novel strategy where the DMA address list is stored inside the FPGA and not in the central memory of the host CPU. The FPGA design package is complemented with simple register access to control the DMA engine by a Linux driver. The design is compatible with Xilinx FPGA Families 6 and 7, and operates with the Xilinx PCIe endpoint Generation 1 and 2 with all lane configurations (x1, x2, x4, x8). A multi-engine architecture is also presented, where two x8 lanes cores are used in parallel together with a PCIe bridge, to exploit fully the capabilities of a PCIe Gen2 x16 lanes link. A data throughput of 3461 MBytes/s has been achieved with a single PCIe Gen2 x8 lanes endpoint. If the dual-engine architecture is used, the throughput is increased up to 6920 MBytes/s. The presented DMA is currently used in several experiments at the ANKA synchrotron light source.

Caselle M., Brosi M., Chilingaryan S., Dritschler T., Judin V., Kopmann A., Mueller A.-S., Raasch J., Smale N.J., Steinmann J., Vogelgesang M., Wuensch S., Siegel M., Weber M.

in 2014 19th IEEE-NPSS Real Time Conference, RT 2014 – Conference Records (2015), 7097535. DOI:10.1109/RTC.2014.7097535

Abstract

© 2014 IEEE. Since a few years Coherent Synchrotron Radiation (CSR) generated by short electron bunches is provided at the ANKA synchrotron light source. To study the THz emission characteristics over multiple revolutions superconducting YBa2Cu3O7-δ (YBCO) thin-film detectors can be used. The intrinsic response time of YBCO thin films is in the order of a few picoseconds only. For fast and continuous sampling of this individual ultra-short terahertz pulses a novel digitizer system has been developed with programmable sampling times in the range of 3 to 100 ps. The Real-time system is based on a heterogeneous FPGA and GPU architecture for on-line pulse reconstruction and evaluations of the peak amplitudes and the time between consecutive bunches. The data is transmitted to a GPU computing node by a fast data transfer link based on a bus master DMA engine connected to PCI express endpoint logic. This new DMA architecture ensures a continuous high data throughput of up to 4 GByte/s. The presented DAQ system is able to resolve the bursting behavior of single bunches even in a multi-bunch environment and to study the bunch-bunch-interactions.

Rota L., Caselle M., Chilingaryan S., Kopmann A., Weber M.

in 2014 19th IEEE-NPSS Real Time Conference, RT 2014 – Conference Records (2015), 7097561. DOI:10.1109/RTC.2014.7097561

Abstract

© 2014 IEEE. PCI Express (PCIe) is a high-speed serial point-to-point interconnect that delivers high-performance data throughput. KIT has developed a Direct Memory Access (DMA) engine compatible with the Xilinx PCIe core to provide a smart and low-occupancy alternative logic to expensive commercial solutions. In order to maximize the PCIe throughput the DMA engine adopts a new strategy, where the DMA descriptor list is stored inside the FPGA and not in the central memory system. The FPGA design package is complemented with a simple register access to control the DMA engine by a Linux driver. A handshaking sequence between the DMA engine and the Linux driver ensures that no errors occure, even in data transfers of several hundreds of Gigabytes. The design has been tested with Xilinx FPGA Families 6 and 7, and operates with the Xilinx PCIe endpoint generation 1 and 2 with all lane configurations (x1, x2, x4, x8, x16). Data throughput of more than 3.4 GB/s has been achieved with a PCIe Gen 2 ×8 lanes endpoint. The proposed DMA is currently used in several experiments at the ANKA synchrotron light source.

Steinmann J.L., Brosi M., Brundermann E., Caselle M., Hertle E., Hiller N., Kehrer B., Muller A.-S., Schonfeldt P., Schuh M., Schutze P., Schwarz M., Hesler J.

in 6th International Particle Accelerator Conference, IPAC 2015 (2015) 1509-1511.

Abstract

Copyright © 2015 CC-BY-3.0 and by the respective authors. Interferometry is the quasi-standard for spectral measurements in the THz- and IR-range. The frequency resolution, however, is limited by the travel range of the interferometer mirrors. Therefore, a resolution in the low megahertz range would require interferometer arms of about 100 m. As an alternative, heterodyne measurements provide a resolution in the Hertz range, an improvement of 6 orders of magnitude. Here we present measurements done at ANKA with a VDI WR3.4SAX, a mixer that can be tuned to frequencies from 220 GHz to 330 GHz and we show how the bunch filling pattern influences the amplitude of specific frequencies.

Brosi M., Caselle M., Hertle E., Hiller N., Kopmann A., Muller A.-S., Schonfeldt P., Schwarz M., Steinmann J.L., Weber M.

in 6th International Particle Accelerator Conference, IPAC 2015 (2015) 882-884.

Abstract

Copyright © 2015 CC-BY-3.0 and by the respective authors. The ANKA storage ring of the Karlsruhe Institute of Technology (KIT) operates in the energy range from 0.5 to 2.5 GeV and generates brilliant coherent synchrotron radiation in the THz range with a dedicated bunch length reducing optic. The producing of radiation in the so-called THz-gap is challenging, but this intense THz radiation is very attractive for certain user experiments. The high degree of compression in this so-called low-alpha optics leads to a complex longitudinal dynamics of the electron bunches. The resulting micro-bunching instability leads to time dependent fluctuations and strong bursts in the radiated THz power. The study of these fluctuations in the emitted THz radiation provides insight into the longitudinal beam dynamics. Fast THz detectors combined with KAPTURE, the dedicated KArlsruhe Pulse Taking and Ultrafast Readout Electronics system developed at KIT, allow the simultaneous measurement of the radiated THz intensity for each bunch individually in a multibunch environment. This contribution gives an overview of the first experience gained using this setup as an online diagnostics tool.