Spillmann U., Blumenhagen K.H., Badura E., Balzer M., Brauning H., Hoffmann J., Koch K., Kurz N., Martin R., Minami S., Ott W., Stohlker T., Weber G., Weber M.

in Physica Scripta, T156 (2013), 014103. DOI:10.1088/0031-8949/2013/T156/014103

Abstract

The future x-ray spectroscopy and polarimetry experiment program of the SPARC collaboration at GSI and FAIR relies strongly on the availability of two-dimensional position-sensitive, energy- and time-dispersive thick semiconductor detector systems, including the appropriate signal processing electronics. To meet these demands, the development of a compact and scalable data acquisition system that has higher rate acceptance compared to commercial VME electronics by employing digital pulse processing electronics was started. © 2013 The Royal Swedish Academy of Sciences.

Balzer M., Kleinert J., Obermayr M.

in Particle-Based Methods III: Fundamentals and Applications – Proceedings of the 3rd International Conference on Particle-based MethodsFundamentals and Applications, Particles 2013 (2013) 920-930.

Abstract

In numerous industrial applications there is the need to realistically model granular material. For instance, simulating the interaction of vehicles and tools with soil is of great importance for the design of earth moving machinery. The Discrete Element Method (DEM) has been successfully applied to this task [1, 2]. Large scale problems require a lot of computational resources. Hence, for the application in the industrial engineering process, the computational effort is an issue. In DEM parallelization is straight forward, since each contact between adjacent particles is resolved locally without regard of the other contacts. However, modelling a contact as a stiff spring imposes strong limitations on the time step size to maintain a stable simulation. The Non-Smooth Contact Dynamics Method (NSCD), on the other hand, models contacts globally as a set of inequality constraints on a system of perfectly rigid bodies [3]. At the end of every time step, all inequality constraints must be satisfied simultaneously, which can be achieved by solving a complementarity problem. This leads to a numerically stable method that is robust with respect to much larger time steps in comparison to DEM. Since a global problem must be solved, parallelization now strongly depends on the numerical solver that is used for the complementarity problem. We present our first massively parallel implementation of NSCD based on the projected Gauß-Jacobi (PGJ) iterative scheme presented in [4]. Focusing on one-sided asynchronous communication patterns with double buffering for data exchange, global synchronizations can be avoided. Only weak synchronization due to data dependencies of neighboring domains remains. The implementation is based on the Global address space Programming Interface (GPI), supplemented by the Multi Core Threading Package (MCTP) [5] on the processor level. This allows to efficiently overlap calculation and communication between processors.

Vergine T., De Matteis M., Rota L., Marchioro A., Baschirotto A.

in Conference Proceedings – 9th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2013 (2013) 45-48, 6603108. DOI:10.1109/PRIME.2013.6603108

Abstract

A calibration circuit for single-ramp A-to-D converters is presented here. The calibration circuit allows to automatically compensate the process/mismatch and radiation effects on the A-to-D converter, improving performance and Equivalent Number of Bits. In particular, the calibration circuit is able to automatically align the ramp signal reference used for the conversion in single slope architectures A-to-D architectures, compensating slope deviations due to technological/electrical reasons. Moreover, the calibration circuit shares the same analog circuits of the A-to-D converter, requiring only a small additional power budget and logic for the implementation. The calibration circuit has been validated, testing the overall A-to-D converter after the calibration. A 12 steps binary search is required to calibrate the A-to-D converter (about 2.5ms). This calibration circuit is able to guarantee an 11bits accuracy, in the worst case simulation corner. The technology used is a 65 nm CMOS. The clock frequency has been set to 20 MHz and the power consumption is about 400 μW. © 2013 IEEE.

Rivetti A., Battaglia M., Bisello D., Caselle M., Chalmet P., Costa M., Demaria N., Giubilato P., Ikemoto Y., Kloukinas K., Mansuy C., Marchioro A., Mugnier H., Pantano D., Potenza A., Rousset J., Silvestrin L., Wyss J.

in Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 730 (2013) 119-123. DOI:10.1016/j.nima.2013.06.068

Abstract

The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400Ωcm, which is at least one order of magnitude greater than the typical value (1-10Ωcm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported. © 2013 Elsevier B.V.

Giubilato P., Battaglia M., Bisello D., Caselle M., Chalmet P., Demaria L., Ikemoto Y., Kloukinas K., Mansuy S.C., Mattiazzo S., Marchioro A., Mugnier H., Pantano D., Potenza A., Rivetti A., Rousset J., Silvestrin L., Snoeys W.

in Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 731 (2013) 146-153. DOI:10.1016/j.nima.2013.04.042

Abstract

The LePix projects aim realizing a new generation monolithic pixel detectors with improved performances at lesser cost with respect to both current state of the art monolithic and hybrid pixel sensors. The detector is built in a 90 nm CMOS process on a substrate of moderate resistivity. This allows charge collection by drift while maintaining the other advantages usually offered by MAPS, like having a single piece detector and using a standard CMOS production line. The collection by drift mechanism, coupled to the low capacitance design of the collecting node made possible by the monolithic approach, provides an excellent signal to noise ratio straight at the pixel cell together with a radiation tolerance far superior to conventional un-depleted MAPS. The excellent signal-to-noise performance is demonstrated by the device ability to separate the 6 keV 55Fe double peak at room temperature. To achieve high granularity (10-20 μm pitch pixels) over large detector areas maintaining high readout speed, a completely new compressing architecture has been devised. This architecture departs from the mainstream hybrid pixel sparsification approach, which uses in-pixel logic to reduce data, by using topological compression to minimize pixel area and power consumption. © 2013 Elsevier B.V.

Caselle M., Chilingaryan S., Herth A., Kopmann A., Stevanovic U., Vogelgesang M., Balzer M., Weber M.

in IEEE Transactions on Nuclear Science, 60 (2013) 3669-3677, 6510495. DOI:10.1109/TNS.2013.2252528

Abstract

X-ray computer tomography is a powerful method for nondestructive investigations in many fields. Three-dimensional images of internal structure are reconstructed from a sequence of two-dimensional projections. The polychromatic high density photon flux of modern synchrotron light sources offer hard X-ray imaging with spatio-temporal resolution up to the micrometer and micrometers range. Existing indirect X-ray image detection systems can be adapted for fast image acquisition by high-speed visible-light cameras. In this paper, we present a platform for custom high-speed CMOS cameras with embedded field-programmable gate array (FPGA) processing. This modular system is characterized by a high-throughput PCI Express (PCIe) interface and efficient communication blocks. It has been used to develop a novel architecture for a self-event trigger that increases the effective image frame rate and reduces the amount of received data. Thanks to a low-noise design, high frame rates in the kilohertz range, and high-throughput data transfer, this camera is well suited for ultrafast synchrotron-based X-ray radiography and tomography. The camera setup is accomplished by high-throughput Linux drivers and a seamless integration in our GPU computing framework. © 2013 British Crown Copyright.

Mattiazzo S., Battaglia M., Bisello D., Caselle M., Chalmet P., Demaria N., Giubilato P., Ikemoto Y., Kloukinas K., Mansuy C., Marchioro A., Mugnier H., Pantano D., Potenza A., Rivetti A., Rousset J., Silvestrin L., Snoeys W., Wyss J.

in Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 718 (2013) 288-291. DOI:10.1016/j.nima.2012.10.098

Abstract

We present a monolithic pixel sensor developed in the framework of the LePIX project aimed at tracking/triggering tasks where high granularity, low power consumption, material budget, radiation hardness and production costs are a concern. The detector is built in a 90 nm CMOS process on a substrate of moderate resistivity. This maintains the advantages usually offered by Monolithic Active Pixel Sensors (MAPS), like a low input capacitance, having a single piece detector and using a standard CMOS production line, but offers charge collection by drift from a depleted region and therefore an excellent signal to noise ratio and a radiation tolerance superior to conventional undepleted MAPS. Measurement results obtained with the first prototypes from laser, radioactive source and beam test experiments are described. The excellent signal-to-noise performance is demonstrated by the capability of the device to separate the peaks in the spectrum of a 55Fe source. We will also highlight the interaction between pixel cell design and architecture which points toward a very precise direction in the development of such depleted monolithic pixel devices for high energy physics. © 2012 Elsevier B.V. All rights reserved.

Potenza A., Bisello D., Caselle M., Costa M., Demaria N., Giubilato P., Ikemoto Y., Mansuy C., Marchioro A., Mattiazzo S., Moll M., Pacher L., Pacifico N., Pantano D., Rivetti A., Silvestrin L., Snoeys W.

in Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 718 (2013) 347-349. DOI:10.1016/j.nima.2012.10.020

Abstract

The LePix project aims at developing monolithic pixel detectors in a 90 nm CMOS technology ported on moderate resistivity substrate. The radiation tolerance of the base material, which is an order of magnitude higher doped than standard high resistivity detectors, and which underwent the full advanced CMOS process, has been investigated. Diodes of about 1 mm2 and pixel matrices were irradiated with neutrons at fluences from 1012 n/cm2 to 2 × 1015 n/cm2 and characterized using CV and IV measurements. Matrices have also been irradiated with Xrays and withstand at least 10 Mrad. © 2012 Elsevier B.V. All rights reserved.

Caselle M., Chilingaryan S., Herth A., Kopmann A., Stevanovic U., Vogelgesang M., Balzer M., Weber M.

in 2012 18th IEEE-NPSS Real Time Conference, RT 2012 (2012), 6418369. DOI:10.1109/RTC.2012.6418369

Abstract

X-ray computed tomography (CT) is a method for non-destructive investigation. Three-dimensional images of internal structure can be reconstructed using a two-dimensional detector. The poly-chromatic high density photon flux in the modern synchrotron light sources offers hard X-ray imaging with a spatio-temporal resolution up to the μm-μs range. Existing indirect X-ray image detectors can be adapted for fast image acquisition by employing CMOS-based digital high speed camera. In this paper, we propose a high-speed visible light camera based on commercial CMOS sensor with embedded processing implemented in FPGA. This platform has been used to develop a novel architecture for a self-event trigger. This feature is able to increase the original frame rate of the CMOS sensor and reduce the amount of the received data. Thanks to a low noise design, high frame rate (kilohertz range) and high speed data transfer, this camera can be employed in modern synchrotron ultra-fast X-ray radiography and computed tomography. The camera setup is accomplished by high-throughput Linux drivers and a seamless integration in our GPU computing framework. Selected applications from life sciences and materials research underline the high potential of this high-speed camera in a hard X-ray micro-imaging approach. © 2012 IEEE.